Traditional RF and microwave amplifiers in use today are GaAs MESFET structures, or discrete silicon MOS and BJT devices. Any amplifier regardless of technology should have reasonable output power drive into a 50 load and low intermodulation distortion since in many applications, systems using these amplifiers in transmitter chains may be operating in close physical proximity to one another. The high input impedance of the MOS transistors presented by the input capacitance C_GS causes the input S-parameter, S₁₁, to be large at low frequencies. The feed forward and output match S-parameters for ideal amplifiers at low frequencies (where the capacitive reactance is negligible) can be written from the equivalent circuit as:

(4)

where g_d is the sum of the driving and current source output conductances. For the ideal amplifier, S₂₂ should be approximately zero which occurs for g_d equal to the inverse of the load impedance. Under this condition, the feed forward term S₂₁ is simply -g_mZ₀.

Class A amplification was chosen in the design because of its high degree of linearity, but at the cost of low efficiency (Figure 6). Each RF amplifier was designed to drive a 50 load with at least 10 dB gain from a high impedance source (such as an on-chip driver). This low resistance load impedance requires physically large FETs since the intrinsic transconductance in CMOS FETs is significantly lower than their bipolar or GaAs counterparts. Each FET in the amplifier utilized a number of separate gate fingers, the actual number depending on the geometry used. These gate fingers were chosen to help reduce the N+-P area and sidewall capacitances of the source and drain diffusions in an effort to improve the frequency response. Each gate finger varied in length depending on the process used, with a total gate width of 5000 m for the 2.0 m process, 3000 m for the 1.2 m and 2000 m for the 0.8 m process. A differential amplifier can be formed simply using two of these basic cells.

RF measurements on the amplifiers were performed up 900 MHz on packaged devices. Figure 7 shows the results of insertion gain measurements and simulations on the 1.2 m RF amplifier. The current source bias (p-FET) and driver bias (n-FET) were varied to achieve the optimum gain. Also shown in Figure 7 are SPICE simulations of the amplifier's gain including test fixture parasitics as well as another set of simulations showing expected amplifier performance in a package more suitable for this amplifier. The 2.0 micron element showed similar low frequency insertion gain but a unity gain frequency of approximately 500 MHz. Measurements also show that the output RF power of these devices is variable (depending on p-FET current source bias) up to +10.5 dBm using a +5.0 volt power supply. The current source bias (p-FET) and driver biases (n-FET) were varied to achieve the optimum gain.

The linearity of the amplifier was determined by a series of distortion measurements taken at 135 MHz on the 1.2 m RF amplifier. The measurement results show second, third and fourth order intermodulation intercept points (referenced to the load) of 44 dBm, 23 dBm and 19 dBm, respectively. With a +10 dBm input power, these distortion intercept points correspond to second, third and fourth order harmonic power levels of -24 dBm, -16 dBm, and -17 dBm, respectively.

Measurements were also taken on a silicon CMOS SPDT switch-RF amplifier configuration feeding a 50 load such as would be seen in an RF front-end application (Figure 1). The bias on the amplifier FETs was adjusted for maximum output power to the load. As expected, the insertion gain of the switch-amplifier combination was reduced by the insertion loss of the switch. The second and third order intercept points of the switch-amplifier combination were reduced from the values presented above by approximately 6 and 3 dB, respectively, primarily due to the distortion properties of the SPDT switch.

Figure 6. CMOS 50 RF amplifier. The same circuit topology was used for all three technologies studied (2.0, 1.2 and 0.8 m).

Figure 7. Frequency Response of the 1.2 m integrated CMOS RF amplifier. Also shown are SPICE simulations of the amplifier's gain including test fixture parasitics as well as another set of simulations showing expected amplifier performance in a typical package more optimized for this amplifier.